Copyright (C) 1994,1995,1996,1997 Terumasa KODAKA, Takeshi KONO
■ AGDC
Target PC-H98
Explanation o AGDC (Advanced Graphics Display Controller: μPD72120) is a graphics
controller installed in the PC-H98 series. Since it is not compatible
with GDC, the PC-H98 series is equipped with both GDC and AGDC.
o Since it is set to draw by GDC at the time of reset, it is necessary
to select the drawing processor as AGDC at I/O port 006Ah when drawing
with AGDC.
o In the PC-H98 series, each register of AGDC is mapped in the range of
I/O 4nAmh (n = upper 4 bits of register number, m = upper 4 bits of register
number).
Related I/O 006Ah - 60h, 61h
I/O 006Ah - 66h, 67h
0000:0458h bit 7
I/O 40A0h, 40A2h
Name Coordinate origin setting
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------
40A0h | WORD | W | EADORG (Execution Address Origin) bits 15 ~ 0
| | | * The lower 16 bits of the absolute address of
| | | the display memory corresponding to the X-Y
| | | coordinates (0,0).
40A2h | WORD | W | bit 15 ~ 12: Unused (set to 0000b)
| | | bit 11 ~ 8: dADORG (Dot Address Origin)
| | | * The dot position in the word set by EADORG
| | | corresponding to the X-Y coordinates (0,0).
| | | bit 7 ~ 0: EADORG bit 23 ~ 16
| | | * The upper 8 bits of the absolute address of the
| | | display memory corresponding to the X-Y
| | | coordinates (0,0).
------------+-------+-----+--------------------------------------------------
I/O 40A4h, 40A6h, 40A8h, 40AAh
Name Absolute address register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
40A4h | WORD | W | EAD1 (Execution Address 1) bits 15 to 0
| | | * Set the lower 16 bits of the drawing start
| | | address when the drawing. Start position is
| | | given by the absolute address.
40A6h | WORD | W | bit 15 ~ 12: Unused (set to 0000b)
| | | bit 11 ~ 8: dAD1 (Dot Address1)
| | | * Specify the dot position in the word set in
| | | EAD1 when the drawing. Start position is given
| | | by the absolute address.
| | | bit 7 ~ 0: EAD1 bit 23 ~ 16
| | | * Set the upper 8 bits of the drawing start
| | | address when the drawing. Start position is
| | | given by the absolute address.
40A8h | WORD | W | EAD2 (Execution Address 2) bits 15 ~ 0
| | | * Set the lower 16 bits of the drawing start
| | | address when the drawing. Start position is
| | | given by the absolute address.
40AAh | WORD | W | bit 15 ~ 12: Unused (set to 0000b)
| | | bit 11 ~ 8: dAD2 (Dot Address2)
| | | * Specify the dot position in the word set in
| | | EAD2 when the drawing. Start position is given
| | | by the absolute address.
| | | bits 7 ~ 0: EAD2 (Execution Address 2) bits 23 to 16
| | | * Set the upper 8 bits of the drawing start address
| | | when the drawing. Start position is given by the
| | | absolute address.
------------+-------+-----+-----------------------------------------------------
I/O 40ACh, 40AEh, 41A0h, 41A2h, 41A4h
Name Interplane drawing register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
40ACh | WORD | W | PDISPS (Plane Displacement Source) bits 15 to 0
40AEh | WORD | W | bit 15 ~ 8: Unused (set to 00h)
| | | bit 7 ~ 0: PDISPS bit 23 ~ 16
41A0h | WORD | W | PDISPD (Plane Displacement Destination) bits 15 to 0
| | | * Set the lower 16 bits of the number of words
| | | occupied by one memory plane
41A2h | WORD | W | bit 15-8: Unused (set to 00h)
| | | bit 7 ~ 0: PDISPD bit 23 ~ 16
| | | * Set the upper 8 bits of the number of words
| | | occupied by one memory plane
41A4h | WORD | W | PMAX (Plane Maximum)
| | | 0000000000000001b = Plain # 0 only
| | | 0000000000000010b = Up to plane # 1
| | | 0000000000000100b = Up to plane # 2
| | | 0000000000001000b = Up to plane # 3
| | | :
| | | :
| | | 0100000000000000b = up to plane # 14
| | | 1000000000000000b = up to plane # 15
| | | * Set which of the maximum 16 planes in the display
| | | memory is to be drawn. Settings other than these
| | | 16 ways are prohibited.
------------+-------+-----+-----------------------------------------------------
I/O 41A6h
Name Logical operation setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
41A6h | WORD | W | bit 15-8: Unused (set to 00h)
| | | bit 7 ~ 4: MOD1 (Drawing Mode1)
| | | bit 3 ~ 0: MOD0 (Drawing Mode 0)
| | | 0000b = D←S REPLACE
| | | 0001b = D←S# REPLACE
| | | 0010b = D←0 REPLACE
| | | 0011b = D←1 REPLACE
| | | 0100b = D←DxorS EXOR
| | | 0101b = D←DxorS# EXOR
| | | 0110b = D←D# EXOR
| | | 0111b = D←D EXOR
| | | 1000b = D←D･S AND
| | | 1001b = D←D･S# AND
| | | 1010b = D←D#･S AND
| | | 1011b = D←D#･S# AND
| | | 1100b = D←D+S OR
| | | 1101b = D←D+S# OR
| | | 1110b = D←D#+S OR
| | | 1111b = D←D#+S# OR
| | | * A register for defining 16 types of logical
| | | operations for each plane set in the logical
| | | operation setting register (I/O 45AEh).
------------+-------+-----+-----------------------------------------------------
I/O 41A8h, 41AAh
Name Line type / fill pattern setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
41A8h | WORD | W | PTNP (Pattern Pointer) bits 15 to 0
| | | * Set the lower 16 bits of the lowest address of the
| | | memory area that stores the fill pattern (tiling
| | | pattern) in the display memory area.
41AAh | WORD | W | bit 15-8: Unused (set to 00h)
| | | bit 7 ~ 0: PTNP bit 23 ~ 16
| | | * In the display memory area, set the upper 8 bits
| | | of the lowest address of the memory area that
| | | stores the fill pattern (tiling pattern).
------------+-------+-----+-----------------------------------------------------
I/O 41ACh, 41AEh
Name Fill stack area setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
41ACh | WORD | W | STACK (Stack Pointer) bits 15 ~ 0
| | | * Set the lower 16 bits of the highest address of
| | | the stack area used when filling an arbitrary
| | | closed area.
41AEh | WORD | W | bit 15-8: Unused (set to 00h)
| | | bit 7 ~ 0: STACK bit 23 ~ 16
| | | * Set the upper 8 bits of the highest address of the
| | | stack area used when filling an arbitrary closed
| | | area.
------------+-------+-----+-----------------------------------------------------
I/O 43ACh
Name STATUS (Status)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
43ACh | WORD | R | bit 15-9: Unused
| | | bit 8: CLP
| | | 1 = Draw in the drawing invalid area
| | | 0 = Normal
| | | bit 7: PGRDY
| | | 1 = Writing to PGPORT is possible when the
| | | PUT / GET command is executed
| | | 0 = Writing to PGPORT is not possible when
| | | executing the PUT / GET command
| | | bit 6: ODDFD
| | | 1 = Odd field during interlaced scan
| | | 0 = Even fields during non-interlaced or
| | | interlaced scans
| | | bit 5: VB
| | | 1 = During Vertical Blanking Interval (VBLANK)
| | | 0 = Vertical Blanking Interval (VBLANK)
| | | Out of Period
| | | bit 4: VS
| | | 1 = During vertical synchronization (VSYNC)
| | | 0 = Out of vertical sync (VSYNC) period
| | | bit 3: DPERR
| | | 1 = Error during execution of drawing processor
| | | processing
| | | 0 = Normal
| | | bit 2: PPERR
| | | 1 = Error during preprocessor processing execution
| | | 0 = Normal
| | | bit 1: DPBSY
| | | 1 = The drawing processor is executing processing
| | | 0 = Normal
| | | bit 0: PPBSY
| | | 1 = Preprocessor is processing
| | | 0 = Normal
------------+-------+-----+-----------------------------------------------------
I/O 43ACh
Name BANK (Bank)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+-----------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+-----------------------------------------------------
43ACh | BYTE | W | BANK
| | | * Display memory Register for address expansion
| | | during direct access. Set 8 bits corresponding to
| | | bit 23 to bit 16 of the display memory address.
------------+-------+-----+-----------------------------------------------------
I/O 43ADh
Name CTRL (Control)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------------
43ADh | BYTE | W | bit 7: DBIE
| | | 1 = Allow busy end interrupt for drawing processor
| | | 0 = Disable busy end interrupt of drawing processor
| | | bit 6: PBIE
| | | 1 = Preprocessor busy termination interrupt enabled
| | | 0 = Preprocessor busy termination interrupt disabled
| | | bit 5: CIE
| | | 1 = Enable interrupt when clipping
| | | 0 = Interrupt interrupt disabled when clipping
| | | bit 4 ~ 2: Unused (to 000b)
| | | bit 1: ABORT
| | | 1 = Forcibly interrupt the processing of the
| | | preprocessor and drawing processor
| | | 0 = Normal
| | | bit 0: RESET
| | | 1 = Software reset
| | | 0 = Normal
------------+-------+-----+--------------------------------------------------------
I/O 43AEh
Name Data port
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------------
43AEh | WORD | R/W | PGPORT (PUT / GET Port)
| | | * Data port used to read and write display memory via
| | | AGDC. When accessing 8 bits, read in order from the
| | | lower 8 bits.
------------+-------+-----+--------------------------------------------------------
I/O 44A0h, 44A2h, 44A4h, 44A6h, 44A8h, 44AAh, 44ACh, 44AEh, 45A0h, 45A2h, 45A4h, 45A6h
Name Coordinate register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------------
44A0h | WORD | W | X
44A2h | WORD | W | Y
44A4h | WORD | W | DX
44A6h | WORD | W | DY
44A8h | WORD | W | XS
44AAh | WORD | W | YS
44ACh | WORD | W | XE
44AEh | WORD | W | YE
45A0h | WORD | W | XC
45A2h | WORD | W | YC
45A4h | WORD | W | DH
45A6h | WORD | W | DV
| | | * Coordinate parameters for performing various drawings
------------+-------+-----+--------------------------------------------------------
I/O 45A8h, 45AAh
Name Memory plane width setting register
Undocumented
Chip AGDC (μPD72120)
I/O
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
45A8h | WORD | W | bit 15 ~ 12: Unused (set to 0000b)
| | | bit 11 ~ 0: PITCHS (Pitch Source)
| | | * Defines the width of the source plane in display memory
45AAh | WORD | W | bit 15-12: Unused (set to 0000b)
| | | bit 11 ~ 0: PITCHD (Pitch Destination)
| | | * Defines the width of the drawing destination plane in
| | | the display memory
------------+-------+-----+----------------------------------------------------------
I/O 45ACh
Name Fill stack area setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
45ACh | WORD | W | STMAX (Stack Maximum)
| | | * Specify the size of the stack area to be used when
| | | filling the optional closed area. However, in 6-word
| | | units.
------------+-------+-----+----------------------------------------------------------
I/O 45AEh
Name Logical operation setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
45AEh | WORD | W | PLANES (Plane Select)
| | | * A register that selects the type of logical operation
| | | to be executed at the time of drawing for each plane.
| | | In a plane set to 0, MOD0 of I/O 41A6h is defined as a
| | | logical operation, and in a plane set to 1, MOD1 of I/O
| | | 41A6h is defined as a logical operation.
------------+-------+-----+----------------------------------------------------------
I/O 45A0h
Name Line type / fill pattern setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
46A0h | WORD | W | PTNCNT (Pattern Count)
------------+-------+-----+----------------------------------------------------------
I/O 46A2h, 46A4h, 46A6h, 46A8h
Name Clipping definition register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
46A2h | WORD | W | XCLMIN (X Clipping Minimum)
46A4h | WORD | W | YCLMIN (Y Clipping Minimum)
46A6h | WORD | W | XCLMAX (X Clipping Maximum)
46A8h | WORD | W | YCLMAX (Y Clipping Maximum)
------------+-------+-----+----------------------------------------------------------
I/O 46ACh
Name Enlargement / reduction setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+------------------------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+------------------------------------------------------------------------
46ACh | WORD | W | bit 15 ~ 10: Unused (set to 000000b)
| | | bit 9,8: CLIP (Clipping Mode)
| | | 00b = Draw only inside the rectangular area
| | | 01b = No clipping
| | | 10b = Draw only outside the rectangular area
| | | 11b = Ban
| | | bit 7 ~ 4: MAGH (Magniufier Horizontal)
| | | * Horizontal magnification when enlarging / reducing drawing
| | | bit 3 ~ 0: MAGV (Magniufier Vertical)
| | | * Vertical magnification when enlarging / reducing drawing
| | | --------------+---------------+---------------+---------------------
| | | Setting value | Enlargement | Reduction | Line width expansion
| | | Setting value | Magnification | Magnification | Magnification
| | | --------------+---------------+---------------+---------------------
| | | 0000b | 16/1 | 1/16 | 1
| | | 0001b | 16/2 | 2/16 | 2
| | | 0010b | 16/3 | 3/16 | 3
| | | 0011b | 16/4 | 4/16 | 4
| | | 0100b | 16/5 | 5/16 | 5
| | | 0101b | 16/6 | 6/16 | 6
| | | 0110b | 16/7 | 7/16 | 7
| | | 0111b | 16/8 | 8/16 | 8
| | | 1000b | 16/9 | 9/16 | 9
| | | 1001b | 16/10 | 10/16 | 10
| | | 1010b | 16/11 | 11/16 | 11
| | | 1011b | 16/12 | 12/16 | 12
| | | 1100b | 16/13 | 13/16 | 13
| | | 1101b | 16/14 | 14/16 | 14
| | | 1110b | 16/15 | 15/16 | 15
| | | 1111b | 16/16 | 16/16 | 16
| | | --------------+---------------+---------------+---------------------
------------+-------+-----+------------------------------------------------------------------------
I/O 46AEh
Name Command register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
46AEh | WORD | W | bit 15-8: COMMNAD (operation code)
| | | 04h = READ_DP (Read Drawing Pointer)
| | | 08h = DOT_D (Dot Direct)
| | | 0Ch = A_DOT_M (Absolute Dot With Move)
| | | 10h = R_DOT_M (Relative Dot With Move)
| | | 14h = A_LINE_M0 (Absolute Line with Move 0)
| | | 18h = A_LINE_M1 (Absolute Line with Move 1)
| | | 1Ch = A_LINE_M2 (Absolute Line with Move 2)
| | | 20h = A_LINE_D0 (Absolute Line Direct 0)
| | | 24h = A_LINE_D1 (Absolute Line Direct 1)
| | | 28h = A_LINE_D2 (Absolute Line Direct 2)
| | | 2Ch = A_LINE_D3 (Absolute Line Direct 3)
| | | 30h = R_LINE_M0 (Relative Line with Move 0)
| | | 32h = R_LINE_M1 (Relative Line with Move 1)
| | | 34h = R_LINE_M2 (Relative Line with Move 2)
| | | 38h = R_LINE_M3 (Relative Line with Move 3)
| | | 3Ch = R_LINE_D0 (Relative Line Direct 0)
| | | 40h = R_LINE_D1 (Relative Line Direct 1)
| | | 44h = R_LINE_D2 (Relative Line Direct 2)
| | | 48h = A_REC (Absolute Rectangle)
| | | 4Ch = R_REC (Relative Rectangle)
| | | 50h = CRL (Circle)
| | | 50h = CRL_FILL (Circle Fill)
| | | 54h = CARC (Circle Arc)
| | | 58h = CSEC (Circle Sector)
| | | 5Ah = CSEG (Circle Segment)
| | | 5Ch = ELPS (Ellipse)
| | | 5Ch = ELPS_FILL (Ellipse_Fill)
| | | 60h = EARC (Ellipse Arc)
| | | 64h = ESEC (Ellipse Sector)
| | | 65h = ESEG (Ellipse Segment)
| | | 68h = PAINT (Paint)
| | | 6Ch = A_TRI_FILL (Absolute Triangle Fill)
| | | 70h = A_TRA_FILL (Absolute Trapezoid Fill)
| | | 74h = R_TRA_FILL (Relative Trapezoid Fill)
| | | 78h = COPY_AA (Copy Address to Address)
| | | 7Ch = COPY_CA (Copy Coordinate to Address)
| | | 80h = COPY_AC (Copy Address to Coordinate)
| | | 84h = COPY_AC (Copy Coordinate to Coordinate)
| | | 8Ch = A_REC_FILL_C
| | | (Absolute Rectangle by Coordinate)
| | | 8Eh = A_REC_FILL_A
| | | (Absolute Rectangle by specified Address)
| | | 90h = R_REC_FILL
| | | (Relative Rectangle Fill by Coordinate)
| | | 94h = PUT_A (Put Data to Address Filed)
| | | 96h = GET_A (Get Data from Address Filed)
| | | 98h = PUT_C (Put Data to Coordinate Filed)
| | | 9Ah = GET_C (Get Data from Coordinate Filed)
| | | 9Ch = READ_COL (Read Color)
| | | bit 7 ~ 0: COMMNAD (operation flag)
| | | * Register to write the command to be executed by AGDC.
| | | The upper 8 bits are the operation code part, and the
| | | lower 8 bits are the operation flag part.
------------+-------+-----+----------------------------------------------------------
I/O 47A0h
Name DISPLAY_CTRL (Display Control)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
47A0h | WORD | W | bit 15: DTM
| | | 1 = Data transfer mode
| | | 0 = Cycle stealing mode
| | | bit 14: DTT
| | | * Output signal of DT # pin in data transfer mode
| | | bit 13 ~ 11: DAD +
| | | * Progress of display address (DAD)
| | | bit 10: IN
| | | 1 = Interlaced display
| | | 0 = Non-interlaced display
| | | bit 9: RE
| | | 1 = Output DRAM refresh address during HSYNC period
| | | 0 = DRAM refresh address is not output
| | | bit 8: SC
| | | 1 = CLK and SCLK are the same
| | | 0 = When the frequency or phase of CLK and SCLK
| | | is different
| | | bit 7: FCCL
| | | 1 = Forced to initialize to even field at the rising
| | | edge of EXVS
| | | 0 = Do not forcibly initialize to even fields at the
| | | rising edge of EXVS
| | | bit 6: TCCL
| | | 1 = Forced to initialize to D1 cycle at the start
| | | of EXVS
| | | 0 = Do not forcibly initialize to D1 cycle at the
| | | start of EXVS
| | | bit 5: MASK
| | | [In master mode]
| | | 1 = Output VSYNC only for even fields when interlaced.
| | | 0 = Output normal VSYNC
| | | [Slave mode]
| | | 1 = Enable EXHS, EXVS input terminals
| | | 0 = Disable EXHS, EXVS input terminal
| | | bit 4: M / S
| | | 1 = Master mode
| | | 0 = Slave mode
| | | bit 3: SD
| | | 1 = Activate BLANK terminal output for all periods
| | | 0 = Activate the BLANK pin output during the
| | | non-display period defined by the sync signal
| | | control circuit.
| | | bit 2: LFI
| | | 1 = When interlaced display, the total number of
| | | lines is odd.
| | | 0 = When interlaced display, the total number of
| | | lines is an even number
| | | bit 1: SPST
| | | 1 = Allow writing of HS, HBP, HH, HD, HFP,
| | | VS, VBP, L/F, VFP
| | | 0 = Initialize the inside in preparation for writing
| | | bit 0: SVS
| | | 1 = Initialize the horizontal / vertical counter at
| | | the rising edge of EXVS
| | | 0 = Do not initialize horizontal / vertical counters
| | | at rising EXVS
------------+-------+-----+----------------------------------------------------------
I/O 47A2h
Name AC (Address Control)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
47A2h | WORD | W | bit 15: Unused
| | | bit 14 ~ 11: AC
| | | bit 10 ~ 0: DISPLAY_PITCH
------------+-------+-----+----------------------------------------------------------
I/O 47A4h, 47A6h, 47ACh
Name WC (Word Count), DAD (Display Address)
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
47A4h | WORD | W | DAD bits 15 ~ 0
47A6h | WORD | W | bit 15 ~ 8: WC bit 7 ~ 0
| | | bit 7 ~ 0: DAD bit 23 ~ 16
47ACh | WORD | W | bit 15-12: WC bits 11-8
| | | bit 11 ~ 0: GCSRYE
| | | (Graphics Cursor Y Coordinate End)
| | | * Y coordinate of graphic Casa display end position
------------+-------+-----+----------------------------------------------------------
I/O 47A8h, 47AAh
Name Casa setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+----------------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+----------------------------------------------------------
47A8h | WORD | W | bit 15: CRS (Cursor Outfigure Select)
| | | 1 = HGCSR and VGSCR output after AND operation
| | | 0 = HGCSR and VGSCR output after OR operation
| | | bit 14: CE (Cursor Display Enable)
| | | 1 = Activate GCSR signal
| | | 0 = Do not activate GCSR signal
| | | bit 13,12: unused
| | | bit 11 ~ 0: GCSRX (Graphics Cursor X Coordinate)
| | | * X coordinate of graphic Casa display start position
47AAh | WORD | W | bit 15-12: Unused
| | | bit 11 ~ 0: GCSRYS
| | | (Graphics Cursor Y Coordinate Start)
| | | * Specify the Y coordinate of the graphic Casa display
| | | start position
------------+-------+-----+----------------------------------------------------------
I/O 47AEh
Name CRT sync signal setting register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------
47AEh | WORD | W | bit 15 ~ 12: Unused (set to 0000b)
| | | bit 11 ~ 0: HS (Horizontal Sync)
| | | HBP (Horizontal Back Porch)
| | | HH (HBP to Center of HS)
| | | HD (Horizontal Display Period)
| | | HFP (Horizontal Front Porch)
| | | VS (Vertical Sync)
| | | VBP (Vertical Back Porch)
| | | L/F (Line / Field)
| | | VFP (Vetrical Front Porch)
------------+-------+-----+--------------------------------------------------
I/O 48A0 ~ 4FAFh
Name Reserved Register
Undocumented
Chip AGDC (μPD72120)
------------+-------+-----+--------------------------------------------------
I/O address | Width | R/W | Contents
------------+-------+-----+--------------------------------------------------
48A0~4FAFh | WORD | R/W | AGDC Reserved Registers
------------+-------+-----+--------------------------------------------------